A semiconductor memory includes a plurality of memory cells. Each memory cell includes a cell transistor and a cell capacitor. The cell transistor is connected between a bit line and a storage node, and turned on in response to a word line. The cell capacitor is connected between the storage node and a terminal of a cell plate voltage.
The storage node has an electrical floating state if the cell transistor is not turned on due to enabling of a word line, and may have 0V similarly to all adjacent nodes before a power is applied. If a power is applied, the cell plate voltage and a voltage of the bit line rise to a ½ level (about 950 mV) of a core voltage VCORE, and a voltage of the word line is maintained to 0V. In this case, a bulk voltage of the cell transistor drops to −0.8V. In this state, the storage node that is connected with the cell plate voltage terminal through the cell capacitor has a voltage level (about 938 mV) slightly lower than a ½ level of the core voltage VCORE.
The above state, in which the voltage level of the storage node becomes the voltage level (about 938 mV) slightly lower than a ½ level of the core voltage VCORE, is maintained until a first active command is input after the power is applied. In other words, if the active command is input so that the word line is in an active state, the state of the storage node may be recognized as ‘0’ state, so that the voltage level of the storage node may be dropped to 0V through the sensing of a sense amplifier.
If the voltage level of the storage node becomes 0V, the cell plate voltage may be level-downed due to the coupling phenomenon of the cell capacitor. Although the level-downed cell plate voltage is recovered to an original voltage level (the ½ level of the core voltage VCORE), since the voltage level of the storage node rises, the ‘0’ data sensing margin is reduced.